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MX25L1605ZM
Macronix NBit TM Memory Family
FEATURES
16M-BIT [x 1] CMOS SERIAL eLiteFlashTM MEMORY - Automatically erases and verifies data at selected
sector - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first) * Status Register Feature * Electronic Identification - JEDEC 2-byte Device ID - RES command, 1-byte Device ID - REMS command, ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first * Additional 4Kb sector independent from main memory for parameter storage to eliminate EEPROM from system HARDWARE FEATURES * SCLK Input
GENERAL * Serial Peripheral Interface (SPI) compatible -- Mode 0 and Mode 3 * 16,777,216 x 1 bit structure * 32 Equal Sectors with 64K byte each - Any sector can be erased * Single Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations * Latch-up protected to 100mA from -1V to Vcc +1V * Low Vcc write inhibit is from 1.5V to 2.5V PERFORMANCE * High Performance - Fast access time: 50MHz serial clock (30pF + 1TTL Load) - Fast program time: 3ms/page (typical, 256-byte per page) - Fast erase time: 1s/sector (typical, 64K-byte per sector) and 32s/chip (typical) - Acceleration mode: - Program time: 2.4ms/page (typical) - Erase time: 0.8s/sector (typical) and 25s/chip (typical) * Low Power Consumption - Low active read current: 30mA (max.) at 50MHz - Low active programming current: 30mA (max.) - Low active erase current: 38mA (max.) - Low standby current: 50uA (max.) - Deep power-down mode 1uA (typical) * Minimum 10K erase/program cycle for array * Minimum 100K erase/program cycle for additional 4Kb SOFTWARE FEATURES * Input Data Format - 1-byte Command code * Auto Erase and Auto Program Algorithm
- Serial clock input
* SI Input - Serial Data Input * SO/PO7 - Serial Data Output or Parallel mode Data output/input * WP#/ACC Pin - Hardware write protection and Program/erase acceleration * HOLD# pin - pause the chip without diselecting the chip (not for paralled mode, please connect HOLD# pin to VCC during parallel mode) * PO0~PO6 - for parallel mode data output/input * PACKAGE - 8-land SON (8x6mm)
P/N: PM1291
REV. 1.0, MAY 16, 2006
1
MX25L1605ZM
GENERAL DESCRIPTION
The MX25L1605 is a CMOS 16,777,216 bit serial eLiteFlashTM Memory, which is configured as 2,097,152 x 8 internally. The MX25L1605 features a serial peripheral interface and software protocol allowing operation on a simple 3- wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). SPI access to the device is enabled by CS# input. The MX25L1605 provide sequential read operation on whole chip. User may start to read from any byte of the array. While the end of the array is reached, the device will wrap around to the beginning of the array and continuously outputs data until CS# goes high. After program/erase command is issued, auto program/ erase algorithms which program/erase and verify the specified page locations will be executed. Program command is executed on a page (256 bytes) basis, and erase command is executed on both chip and sector (64K bytes) basis. To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion and error flag status of a program or erase operation. To increase user's factory throughputs, a parallel mode is provided. The performance of read/program is dramatically improved than serial mode on programmer machine. When the device is not in operation and CS# is high, it is put in standby mode and draws less than 50uA DC current. The additional 4Kb sector with 100K erase/program endurance cycles is suitable for parameter storage and replaces the EEPROM on system. The MX25L1605 utilizes MXIC's proprietary memory cell which reliably stores memory contents even after 10K program and erase cycles.
PIN CONFIGURATIONS
8-LAND SON (8x6mm small outline no-lead)
PIN DESCRIPTION
SYMBOL CS# SI SO/PO7(1) SCLK HOLD#(2) WP#/ACC DESCRIPTION Chip Select Serial Data Input Serial Data Output or Parallel Data output/input Clock Input Hold, to pause the serial communication (HOLD# is not for parallel mode) Write Protection: connect to GND; 12V for program/erase acceleration: connect to 12V + 3.3V Power Supply Ground Parallel data output/input (PO0~PO6 can be connected to NC in serial mode) No Internal Connection
CS# SO WP# GND
1 2 3 4
8 7 6 5
VCC HOLD# SCLK SI
VCC GND PO0~PO6 NC
Note: HOLD# is recommended to connect to VCC during parallel mode.
P/N: PM1291
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MX25L1605ZM
BLOCK DIAGRAM
additional 4Kb
Address Generator
X-Decoder
Memory Array
SI
Data Register Y-Decoder SRAM Buffer Sense Amplifier HV Generator SO Output Buffer
CS#, ACC, WP#,HOLD#
Mode Logic
State Machine
SCLK
Clock Generator
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DATA PROTECTION
The MX25L1605 are designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise. * Power-On Reset and an internal timer (tPUW) can provide protection against inadvertant changes while the power supply is outside the operating specification. * Program, Erase and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. * To avoid unexpected changes by system power supply transition, the Power-On Reset and an internal timer (tPUW) can protect the device. * Before the Program, Erase, and Write Status Register execution, instruction length will be checked on following the clock pulse number to be multiple of eight base. * Write Enable (WREN) instruction must set to Write Enable Latch (WEL) bit before writing other instructions to modify data. The WEL bit will return to reset state by following situations: - Power-up - Write Disable (WRDI) instruction completion - Write Status Register (WRSR) instruction completion - Page Program (PP) instruction completion - Sector Erase (SE) instruction completion - Chip Erase (CE) instruction completion * The Software Protected Mode (SPM) use (BP2, BP1, BP0) bits to allow part of memory to be protected as read only. * The Hardware Protected Mode (HPM) use WP# to protect the (BP2, BP1, BP0) bits and SRWD bit. * Deep-Power Down Mode also protects the device by ignoring all instructions except Release from DeepPower Down (RDP) instruction and RES instruction.
* All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit . This bit is returned to its reset state by the following events: - Power-up - Write Disable (WRDI) instruction completion - Write Status Register (WRSR) instruction completion - Page Program (PP) instruction completion - Sector Erase (SE) instruction completion - Chip Erase (CE) instruction completion * The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as readonly. This is the Software Protected Mode (SPM). The Write Protect (WP#) signal allows the Block Protect (BP2, BP1, BP0) bits and Status Register Write Disable (SRWD) bit to be protected. This is the Hardware Protected Mode (HPM). In addition to the low power consumption feature, the Deep Power-down mode offers extra software protection from inadvertent Write, Program and Erase instructions, as all instructions are ignored except one particular instruction (the Release from Deep Powerdown instruction).
*
*
P/N: PM1291
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Table 1. Protected Area Sizes
Status bit BP2 0 0 0 0 1 1 1 1 BP1 0 0 1 1 0 0 1 1 BP0 0 1 0 1 0 1 0 1 Protection Area 16Mb None Upper 32nd (Sector 31) Upper sixteenth (two sectors: 30 and 31) Upper eighth (four sectors: 28 to 31) Upper quarter (eight sectors: 24 to 31) Upper half (sixteen sectors: 16 to 31) All All
Note: 1. The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.
P/N: PM1291
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HOLD FEATURE
HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the operation of write status register, programming, or erasing in progress. The operation of HOLD requires Chip Select(CS#) keeping low and starts on falling edge of HOLD# pin signal while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Serial Clock(SCLK) signal is being low( if Serial Clock signal is not being low, HOLD operation will not end until Serial Clock being low), see Figure 1.
Figure 1. Hold Condition Operation
SCLK
HOLD#
Hold Condition (standard use)
Hold Condition (non-standard use)
The Serial Data Output (SO) is high impedance, both Serial Data Input (SI) and Serial Clock (SCLK) are don't care during the HOLD operation. If Chip Select (CS#) signal goes high during HOLD operation, it has the effect on resetting the internal logic of the device. It is necessary to drive HOLD# signal to high, and then to drive CS# to low for restarting communication with the device. The HOLD operation is not recommended to use during parallel mode.
PROGRAM/ERASE ACCELERATION
To activate the program/erase acceleration function requires ACC pin connecting to 12V voltage (see Figure 2), and then to be followed by the normal program/erase process. By utilizing the program/erase acceleration operation, the performances are improved as shown on table of "ERASE AND PROGRAM PERFORMACE".
Figure 2. ACCELERATED PROGRAM TIMING DIAGRAM
12V
VHH
ACC
VIL or VIH tVHH tVHH
VIL or VIH
Note: tVHH (VHH Rise and Fall Time) min. 250ns
P/N: PM1291
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REV. 1.0, MAY 16, 2006
MX25L1605ZM
Table 2. COMMAND DEFINITION
COMMAND WREN (byte) (write Enable) 1st 06 Hex 2nd 3rd 4th 5th Action sets the (WEL) write enable latch bit WRDI (write disable) 04 Hex RDID (read identification) 9F Hex RDSR (read status register) 05 Hex WRSR READ (write status (read data) register) 01 Hex 03 Hex AD1 AD2 AD3 to write new n bytes values to the read out status register until CS# goes high Fast Read Parallel (fast read Mode data) 0B Hex 55 Hex AD1 AD2 AD3 x Enter and stay in Parallel Mode until power off REMS (Read Electronic Manufacturer & Device ID) 90 Hex x x ADD (1) Output the manufacturer ID and device ID
reset the (WEL) write enable latch bit
output the to read out manufacturer the status ID and 2-byte register device ID
COMMAND SE CE (byte) (Sector (Chip Erase) Erase) 1st 2nd 3rd 4th 5th Action 20 or D8 Hex AD1 AD2 AD3 60 or C7 Hex
PP DP (Page (Deep Program) Power Down) 02 Hex B9 Hex AD1 AD2 AD3
EN4K (Enter 4Kb sector) A5 Hex
EX4K (Exit 4Kb sector) B5 Hex
RDP RES(Read (Release Electronic from Deep ID) Power-down) AB Hex AB Hex x x x
Enter the additional 4Kb sector
Exit the additional 4Kb sector
(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first
P/N: PM1291
7
REV. 1.0, MAY 16, 2006
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Table 3. Memory Organization
Sector 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Range 1F0000h 1FFFFFh 1E0000h 1EFFFFh 1D0000h 1DFFFFh 1C0000h 1CFFFFh 1B0000h 1BFFFFh 1A0000h 1AFFFFh 190000h 19FFFFh 180000h 18FFFFh 170000h 17FFFFh 160000h 16FFFFh 150000h 140000h 130000h 120000h 110000h 100000h 15FFFFh 14FFFFh 13FFFFh 12FFFFh 11FFFFh 10FFFFh Sector 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Range 0F0000h 0FFFFFh 0E0000h 0EFFFFh 0D0000h 0DFFFFh 0C0000h 0CFFFFh 0B0000h 0BFFFFh 0A0000h 0AFFFFh 090000h 09FFFFh 080000h 08FFFFh 070000h 07FFFFh 060000h 06FFFFh 050000h 05FFFFh 040000h 04FFFFh 030000h 03FFFFh 020000h 02FFFFh 010000h 01FFFFh 000000h 00FFFFh
P/N: PM1291
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DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation. 2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z. 3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next CS# rising edge. 4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK. The difference of SPI mode 0 and mode 3 is shown as Figure 3. Figure 3. SPI Modes Supported
CPOL CPHA SCLK
(SPI mode 0)
0
0
(SPI mode 3)
1
1
SCLK
SI
MSB
SO
MSB
5. For the following instructions: RDID, RDSR, READ, FAST_READ, RES, and REMS-the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, Parallel Mode, SE, CE, PP, EN4K, EX4K, RDP and DP the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglected and not affect the current operation of Write Status Register, Program, Erase.
P/N: PM1291
9
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COMMAND DESCRIPTION (1) Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, SE, CE, and WRSR, which are intended to change the device content, should be set every time after the WREN instruction setting the WEL bit. The sequence of issuing WREN instruction is: CS# goes low-> sending WREN instruction code-> CS# goes high. (see Figure 12)
(2) Write Disable (WRDI)
The Write Disable (WRDI) instruction is for re-setting Write Enable Latch (WEL) bit. The sequence of issuing WRDI instruction is: CS# goes low-> sending WRDI instruction code-> CS# goes high. (see Figure 13) The WEL bit is reset by following situations: - Power-up - Write Disable (WRDI) instruction completion - Write Status Register (WRSR) instruction completion - Page Program (PP) instruction completion - Sector Erase (SE) instruction completion - Chip Erase (CE) instruction completion
(3) Read Identification (RDID)
The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC Manufacturer ID is C2(hex), the memory type ID is 20(hex) as the first-byte device ID, and the individual device ID of second-byte ID is as followings: 15(hex) for MX25L1605. The sequence of issuing RDID instruction is: CS# goes low-> sending RDID instruction code -> 24-bits ID data out on SO -> to end RDID operation can use CS# to high at any time during data out. (see Figure. 14) While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.
P/N: PM1291
10
REV. 1.0, MAY 16, 2006
MX25L1605ZM
(4) Read Status Register (RDSR)
The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress. The sequence of issuing RDSR instruction is: CS# goes low-> sending RDSR instruction code-> Status Register data out on SO (see Figure. 15) The definition of the status register bits is as below: WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction.
BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area(as defined in table 1) of the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect (BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), and Chip Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed)
Program/erase error bit. When the program/erase bit set to 1, there is an error occurred in last program/erase operation. The Flash may accept a new program/erase command to re-do program/erase operation.
SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection (WP#) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP# pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP2, BP1, BP0) are read only. bit 7 SRWD Status Register Write Protect 1= status register write disable bit 6 Program/ erase error 1=error bit 5 0 bit 4 bit 3 bit 2 BP2 BP1 BP0 the level of the level of the level of protected protected protected block block block (note 1) (note 1) (note 1) bit 1 WEL (write enable latch) bit 0 WIP (write in progress bit)
1=write enable 1=write operation 0=not write 0=not in write enable operation
Note: 1. See the table "Protected Area Sizes".
P/N: PM1291
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MX25L1605ZM
(5) Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP2, BP1, BP0) bits to define the protected area of memory (as shown in table 1). The WRSR also can set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#) pin signal. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered. The sequence of issuing WRSR instruction is: CS# goes low-> sending WRSR instruction code-> Status Register data on SI-> CS# goes high. (see Figure 16) The WRSR instruction has no effect on b6, b5, b1, b0 of the status register. The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. The selftimed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset.
Table 4. Protection Modes
WP# Signal 1 0 SRWD Bit 0 0 Software Protected (SPM) Mode Write Protection of the Status Register Status Register is Writable (if the WREN instruction has set the WEL bit) The values in the SRWD, BP2, BP1 and BP0 bits can be changed Status Register is Hardware write protected The values in the SRWD, BP2, BP1 and BP0 bits cannot be changed Memory Content Protected Area1 Unprotected Area1
Protected against Page Program, Sector Erase and Chip Erase
Ready to accept Page Program and Sector Erase instructions
1
1
0
1
Hardware Protected (HPM)
Protected against Page Program, Sector Erase and Chip Erase
Ready to accept Page Program and Sector Erase instructions
Note: 1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 1.
As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM). Software Protected Mode (SPM): - When SRWD bit=0, no matter WP# is low or high, the WREN instruction may set the WEL bit and can change the values of SRWD, BP2, BP1, BP0. The protected area, which is defined by BP2, BP1, BP0, is at software protected mode (SPM). - When SRWD bit=1 and WP# is high, the WREN instruction may set the WEL bit can change the values of SRWD, BP2, BP1, BP0. The protected area, which is defined by BP2, BP1, BP0, is at software protected mode (SPM)
P/N: PM1291
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Note: If SRWD bit=1 but WP# is low, it is impossible to write the Status Register even if the WEL bit has previously been set. It is rejected to write the Status Register and not be executed. Hardware Protected Mode (HPM): - When SRWD bit=1, and then WP# is low (or WP# is low before SRWD bit=1), it enters the hardware protected mode (HPM). The data of the protected area is protected by software protected mode by BP2, BP1, BP0 and hardware protected mode by the WP# to against data modification. Note: to exit the hardware protected mode requires WP# driving high once the hardware protected mode is entered. If the WP# pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via BP2, BP1, BP0.
(6) Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing READ instruction is: CS# goes low-> sending READ instruction code-> 3-byte address on SI -> data out on SO-> to end READ operation can use CS# to high at any time during data out. (see Figure. 17)
(7) Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing FAST_READ instruction is: CS# goes low-> sending FAST_READ instruction code-> 3-byte address on SI-> 1-dummy byte address on SI->data out on SO-> to end FAST_READ operation can use CS# to high at any time during data out. (see Figure. 18) While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.
(8) Parallel Mode (Highly recommended for production throughputs increasing)
The parallel mode provides 8 bit inputs/outputs for increasing throughputs of factory production purpose. The parallel mode requires 55H command code, after writing the parallel mode command and then CS# going high, after that, the eLiteFlashTM Memory can be available to accept read/program/read status/read ID/RES/REMS command as the normal writing command procedure. The eLiteFlashTM Memory will be in parallel mode until VCC power-off. a. Only effective for Read Array for normal read(not FAST_READ), Read Status, Read ID, Page Program, RES and REMS write data period. (refer to Figure 29~34) b. For normal write command (by SI), No effect c. Under parallel mode, the fastest access clock freq. will be changed to 1.5MHz(SCLK pin clock freq.) d. For parallel mode, the tAA will be change to 50ns.
P/N: PM1291 REV. 1.0, MAY 16, 2006
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MX25L1605ZM
(9) Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector (see table 3) is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing SE instruction is: CS# goes low -> sending SE instruction code-> 3-byte address on SI -> CS# goes high. (see Figure 20) The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the page.
(10) Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). Any address of the sector (see table 3) is a valid address for Chip Erase (CE) instruction. The CS# must go high exactly at the byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing CE instruction is: CS# goes low-> sending CE instruction code-> CS# goes high. (see Figure 21) The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tBE timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is protected by BP2, BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when BP2, BP1, BP0 all set to "0".
(11) Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). If the eight least significant address bits (A7-A0) are not all 0, all transmitted data which goes beyond the end of the current page are programmed from the start address if the same page (from the address whose 8 least significant address bits (A7-A0) are all 0). The CS# must keep during the whole Page Program cycle. The CS# must go high exactly at the byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. If more than 256 bytes are sent to the device, the data of the last 256-byte is programmed at the request page and previous data will be disregarded. If less than 256 bytes are sent to the device, the data is programmed at the request address of the page without effect on other address of the same page. The sequence of issuing PP instruction is: CS# goes low-> sending PP instruction code-> 3-byte address on SI-> at least 1-byte on data on SI-> CS# goes high. (see Figure 19) The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed.
P/N: PM1291
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(12) Enter 4Kbit Mode (EN4K) and Exit 4Kbit Mode (EX4K)
Enter and Exit 4kbit mode (EN4K & EX4K) (see Figure 27 & 28) EN4K and EX4K will not be executed when the chip is in busy state. Enter 4kbit mode then the read and write command will be executed on this 4kbit. All read and write command sequence is the same as the normal array. The address of this 4k bits is: A20~A9=0 and A8~A0 customer defined. Note 1: Chip erase and WRSR will not be executed in 4kbit mode. During Enter 4Kbit Mode, the following instructions can be accepted: WREN, WRDI, RDID, RDSR, FAST_READ, READ, SE, PP, DP, RDP, RES, REMS. Note 2: Chip erase can't erase this 4kbit About the fail status: Bit6 of the status register is used to state fail status, bit6=1 means program or erase have been failed. Any new write command will clear this bit.
(13) Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to entering the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/ Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep power-down mode. It's different from Standby mode. The sequence of issuing DP instruction is: CS# goes low-> sending DP instruction code-> CS# goes high. (see Figure 22) Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP) and Read Electronic Signature (RES) instruction. (RES instruction to allow the ID been read out). When Power-down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2.
(14) Release from Deep Power-down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Powerdown mode, the transition to the Stand-by Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip Se-lect (CS#) must remain High for at least tRES2(max), as specified in Table 6. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new deisng, please use RDID instruction. Even in Deep power-down mode, the RDP, RES, and REMS are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress. The sequence is shown as Figure 23,24,25. The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if
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continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in Deep Powerdown mode, the device transition to standby mode is immediate. If the device was previously in Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. The RDP instruction is for releasing from Deep Power Down Mode.
(15) Read Electronic Manufacturer ID & Device ID (REMS)
The REMS instruction is an alternative to the Release from Power-down/Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. The REMS instruction is very similar to the Release from Power-down/Device ID instruction. The instruction is initiated by driving the CS# pin low and shift the instruction code "90h" followed by two dummy bytes and one bytes address (A7~A0). After which, the Manufacturer ID for MXIC (C2h) and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in figure 25. The Device ID values are listed in Table of ID Definitions on page 20. If the one-byte address is initially set to 01h, then the device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high.
Table of ID Definitions: RDID Command RES Command REMS Command manufacturer ID C2 manufacturer ID C2 memory type 20 electronic ID 14 device ID 14 memory density 15
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POWER-ON STATE
At Power-up and Power-down, the device must not be selected (that is Chip Select (CS#) must follow the voltage applied on VCC) until VCC reaches the correct value: - VCC(min) at Power-up, and then for a further delay of tVSL - VSS at Power-down Usually a simple pull-up resistor on Chip Select (CS#) can be used to insure safe and proper Power-up and Power-down. To avoid data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less than the POR threshold value, VWI --all operations are disabled, and the device does not respond to any instruction. Moreover, the device ignores all Write Enable (WREN), Page Program (PP), Sector Erase (SE), Chip Erase (CE) and Write Status Register (WRSR) instructions until a time delay of tPUW has elapsed after the moment that VCC rises above the VWI threshold. However, the correct operation of the device is not guaranteed if, by this time, VCC is still below VCC(min). No Write Status Register, Program or Erase instructions should be sent until the later of: - tPUW after VCC passed the VWI threshold - tVSL after VCC passed the VCC(min) level These values are specified in Table 7. If the delay, tVSL, has elapsed, after VCC has risen above VCC(min), the device can be selected for READ instructions even if the tPUW delay is not yet fully elapsed. At Power-up, the device is in the following state: - The device is in the Standby mode (not the Deep Power-down mode). - The Write Enable Latch (WEL) bit is reset. Normal precautions must be taken for supply rail decoupling, to stabilize the VCC feed. Each device in a system should have the VCC rail decoupled by a suitable capacitor close to the package pins. (Generally, this capacitor is of the order of 0.1uF). At Power-down, when VCC drops from the operating voltage, to below the POR threshold value, VWI, all operations are disabled and the device does not respond to any instruction. (The designer needs to be aware that if a Power-down occurs while a Write, Program or Erase cycle is in progress, some data corruption can result.)
P/N: PM1291
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ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS
RATING VALUE Industrial grade 0C to 70C for Commercial grade Storage Temperature Applied Input Voltage Applied Output Voltage VCC to Ground Potential -55C to 125C -0.5V to 4.6V -0.5V to 4.6V -0.5V to 4.6V Ambient Operating Temperature -40C to 85C for NOTICE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. 2. Specifications contained within the following tables are subject to change. 3. During voltage transitions, all pins may overshoot to 4.6V or -0.5V for period up to 20ns. 4. All input and output pins may overshoot to VCC+0.5V while VCC+0.5V is smaller than or equal to 4.6V.
Figure 4.Maximum Negative Overshoot Waveform
Figure 5. Maximum Positive Overshoot Waveform
20ns
0V -0.5V
4.6V 3.6V
20ns
CAPACITANCE TA = 25C, f = 1.0 MHz
SYMBOL CIN COUT PARAMETER Input Capacitance Output Capacitance MIN. TYP MAX. 10 10 UNIT pF pF CONDITIONS VIN = 0V VOUT = 0V
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Figure 6. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL
Input timing referance level 0.8VCC 0.7VCC 0.3VCC 0.2VCC AC Measurement Level Output timing referance level
0.5VCC
Note: Input pulse rise and fall time are <5ns
Figure 7. OUTPUT LOADING
DEVICE UNDER TEST
2.7K ohm +3.3V
CL
6.2K ohm
DIODES=IN3064 OR EQUIVALENT
CL=30pF Including jig capacitance
P/N: PM1291
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Table 5. DC CHARACTERISTICS (Temperature = -40C to 85C for Industrial grade, Temperature = 0C to 70C for Commercial grade, VCC = 2.7V ~ 3.6V)
SYMBOL PARAMETER ILI ILO ISB1 ISB2 ICC1 Input Load Current Output Leakage Current VCC Standby Current Deep Power-down Current VCC Read 1 30 30 10 20 ICC2 ICC3 VCC Program Current (PP) VCC Write Status Register (WRSR) Current ICC4 ICC5 VHH VIL VIH VOL VOH VCC Sector Erase Current (SE) VCC Chip Erase Current (CE) Voltage for ACC Program Acceleration Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VCC-0.2 -0.5 0.7VCC 0.3VCC VCC+0.4 0.4 V V V V IOL = 1.6mA IOH = -100uA 1 11.5 12.5 V 1 38 mA 1 38 mA Erase in Progress CS#=VCC Erase in Progress CS#=VCC VCC=2.7V~3.6V 30 mA 1 30 mA mA mA mA mA 1 10 uA 1 50 uA 1 2 uA NOTES 1 MIN. TYP MAX. 2 UNITS uA TEST CONDITIONS VCC = VCC Max VIN = VCC or GND VCC = VCC Max VIN = VCC or GND VIN = VCC or GND CS# = VCC VIN = VCC or GND CS# = VCC f=50MHz (serial) f=1.5MHz (parallel) f=20MHz (serial) f=1.2MHz (parallel) Program in Progress CS# = VCC Program status register in progress CS#=VCC
NOTES: 1. Typical values at VCC = 3.3V, T = 25C. These currents are valid for all product versions (package and speeds). 2. Typical value is calculated by simulation.
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Table 6. AC CHARACTERISTICS (Temperature = -40C to 85C for Industrial grade, Temperature = 0C to 70C for Commercial grade, VCC = 2.7V ~ 3.6V)
Symbol fSCLK Parameter Clock Frequency for the following instructions: Serial FAST_READ, PP, SE, BE, DP, RES,REMS, RDP WREN, WRDI, RDID, RDSR, WRSR, EN4K, EX4K Parallel fR Clock Frequency for READ instructions Serial Parallel tCLH Clock High Time Serial Parallel tCLL Clock Low Time Serial Parallel Clock Rise Time (3) (peak to peak) Serial Parallel Clock Fall Time (3) (peak to peak) Serial Parallel tCSS S Active Setup Time (relative to C) S Not Active Hold Time (relative to C) tDSU Data In Setup Time tDH Data In Hold Time S Active Hold Time (relative to C) S Not Active Setup Time (relative to C) tCSH S Deselect Time tDIS Output Disable Time tV Clock Low to Output Valid tHO Output Hold Time HOLD# Setup Time (relative to C) HOLD# Hold Time (relative to C) HOLD Setup Time (relative to C) HOLD Hold Time (relative to C) tLZ HOLD to Output Low-Z tHZ HOLD# to Output High-Z Write Protect Setup Time Write Protect Hold Time S High to Deep Power-down Mode S High to Standby Mode without Electronic Signature Read S High to Standby Mode with Electronic Signature Read Write Status SRWD, BP2, BP1, BP0 Register Cycle Time WIP, WEL Page Program Cycle Time Sector Erase Cycle Time Chip Erase Cycle Time Alt. fC Min. D.C. Typ. Max. 50 1.5 20 1.2 Unit MHz MHz MHz MHz ns ns ns ns V/ns V/ns V/ns V/ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ms ms ns ms s s
fRSCLK tCH(1) tCL(1) tCLCH(2) tCHCL(2) tSLCH tCHSL tDVCH tCHDX tCHSH tSHCH tSHSL tSHQZ(2) tCLQV tCLQX tHLCH tCHHH tHHCH tCHHL tHHQX(2) tHLQZ(2) tWHSL(4) tSHWL(4) tDP(2) tRES1(2) tRES2(2) tW tPP tSE tCE
D.C. 9 180 9 180 0.1 2 0.1 2 5 5 2 5 5 5 100
8 8 0 5 5 5 5 8 8 20 100 3 30 30 500 30 12 3 64
90 20 3 1 32
Note: 1. tCH + tCL must be greater than or equal to 1/ fC 2. Value guaranteed by characterization, not 100% tested in production. 3. Expressed as a slew-rate. 4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. 5. Test condition is shown as Figure 3.
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Table 7. Power-Up Timing and VWI Threshold
Symbol tVSL(1) tPUW(1) VWI(1) Parameter VCC(min) to S low Time delay to Write instruction Write Inhibit Voltage Min. 30 1 1.5 Max. 10 2.5 Unit us ms V
Note: 1. These parameters are characterized only.
INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0).
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Figure 8. Serial Input Timing
tSHSL CS# tCHSL SCLK tDVCH tCHDX SI MSB IN tCLCH LSB IN tCHCL tSLCH tCHSH tSHCH
SO
High Impedance
Figure 9. Write Protect Setup and Hold Timing during WRSR when SRWD=1
WP# tWHSL tSHWL
CS#
SCLK
SI High Impedance SO
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Figure 10. Hold Timing
CS# tHLCH tCHHL SCLK tCHHH tHLQZ SO tHHQX tHHCH
SI
HOLD#
Figure 11. Output Timing
CS# tCH SCLK tCLQV tCLQX SO tQLQH tQHQL SI
ADDR.LSB IN
tCLQV tCLQX
tCL
tSHQZ
LSB OUT
P/N: PM1291
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Figure 12. Write Enable (WREN) Instruction Sequence
CS# 0 SCLK Instruction SI 1 2 3 4 5 6 7
High Impedance SO
Figure 13. Write Disable (WRDI) Instruction Sequence
CS# 0 SCLK Instruction SI 1 2 3 4 5 6 7
High Impedance SO
Figure 14. Read Identification (RDID) Instruction Sequence and Data-Out Sequence
CS# 0 SCLK Instruction SI Manufacturer Identification High Impedance SO
X7
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
28 29 30 31
Device Identification 3 2 1 0
6
5
3
2
1
0 15 14 13 MSB
MSB
Notes: In serial RDID and RDSR mode, output pin SO will be enabled at 8th clock's rising edge. That means, MXIC's drip will enable output half a cycle in advance compare with other compatible vendor's spec.
P/N: PM1291 REV. 1.0, MAY 16, 2006
25
MX25L1605ZM
Figure 15. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence
CS# 0 SCLK Instruction SI Status Register Out High Impedance SO
X7
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Status Register Out 0 7 MSB 6 5 4 3 2 1 0 7
6
5
4
3
2
1
MSB
Notes: In serial RDID and RDSR mode, output pin SO will be enabled at 8th clock's rising edge. That means, MXIC's drip will enable output half a cycle in advance compare with other compatible vendor's spec.
Figure 16. Write Status Register (WRSR) Instruction Sequence
CS# 0 SCLK Instruction Status Register In 7 High Impedance SO MSB 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SI
Figure 17. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence
CS# 0 SCLK Instruction 24-Bit Address 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
SI High Impedance SO
23 22 21 MSB
3
2
1
0 Data Out 1
X
Data Out 2 1 0 7
7
6
5
4
3
2
MSB
Notes: In READ mode, FAST_READ mode, RES mode and REMS mode, MXIC IC will enable output an entire cycle in advance compare with other compatible vendor's spec. Detail condition please reference the waveform.
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Figure 18. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Out Sequence
CS# 0 SCLK Instruction 24 BIT ADDRESS 1 2 3 4 5 6 7 8 9 10 28 29 30 31
SI
23 22 21
3
2
1
0
SO
High Impedance
CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Byte
SI
7
6
5
4
3
2
1
0 DATA OUT 1 DATA OUT 2 1 0 7 MSB 6 5 4 3 2 1 0 7 MSB
SO
X
7 MSB
6
5
4
3
2
Notes: In READ mode, FAST_READ mode, RES mode and REMS mode, MXIC IC will enable output an entire cycle in advance compare with other compatible vendor's spec. Detail condition please reference the waveform.
P/N: PM1291
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Figure 19. Page Program (PP) Instruction Sequence
CS# 0 SCLK Instruction 24-Bit Address Data Byte 1 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
SI
23 22 21 MSB
3
2
1
0
7
6
5
4
3
2
1
0
MSB
CS#
2072 2073 2074 2075 2076 2077 2078
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SCLK Data Byte 2 Data Byte 3
Data Byte 256
SI
7
6
5
4
3
2
1
0
7 MSB
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
Figure 20. Sector Erase (SE) Instruction Sequence
CS# 0 SCLK Instruction 24 Bit Address 1 2 3 4 5 6 7 8 9 29 30 31
SI
23 22 MSB
2
1
0
Note: SE instruction is 20(hex) or D8(hex).
P/N: PM1291
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MX25L1605ZM
Figure 21. Chip Erase (CE) Instruction Sequence
CS# 0 SCLK Instruction SI 1 2 3 4 5 6 7
Note: CE instruction is 60(hex) or C7(hex).
Figure 22. Deep Power-down (DP) Instruction Sequence
CS# 0 SCLK Instruction SI 1 2 3 4 5 6 7 tDP
Stand-by Mode
Deep Power-down Mode
Figure 23. Release from Deep Power-down and Read Electronic Signature (RES) Instruction Sequence and Data-Out Sequence
CS# 0 SCLK Instruction 3 Dummy Bytes tRES2 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38
SI
23 22 21 MSB High Impedance
3
2
1
0 Electronic Signature Out
X
SO
7 MSB
6
5
4
3
2
1
0
Deep Power-down Mode
Stand-by Mode
Notes: In READ mode, FAST_READ mode, RES mode and REMS mode, MXIC IC will enable output an entire cycle in advance compare with other compatible vendor's spec. Detail condition please reference the waveform.
P/N: PM1291
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Figure 24. Release from Deep Power-down (RDP) Instruction Sequence
CS# 0 SCLK Instruction SI 1 2 3 4 5 6 7 tRES1
High Impedance SO
Deep Power-down Mode
Stand-by Mode
Figure 25. Read Electronic Manufacturer & Device ID (REMS) Instruction Sequence and Data-Out Sequence
CS# 0 SCLK Instruction 2 Dummy Bytes 1 2 3 4 5 6 7 8 9 10
SI
15 14 13
3
2
1
0
SO
High Impedance
CS# 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK ADD (1)
SI
7
6
5
4
3
2
1
0 Manufacturer ID Device ID 0 7 MSB 6 5 4 3 2 1 0 7 MSB
SO
X
7 MSB
6
5
4
3
2
1
Notes: (1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first (2) In READ mode, FAST_READ mode, RES mode and REMS mode, MXIC IC will enable output an entire cycle in advance compare with other compatible vendor's spec. Detail condition please reference the waveform.
P/N: PM1291
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Figure 26. Power-up Timing
VCC VCC(max) Program, Erase and Write Commands are Rejected by the Device Chip Selection Not Allowed VCC(min) Reset State of the Device VWI tPUW tVSL Read Access allowed Device fully accessible
time
P/N: PM1291
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MX25L1605ZM
Figure 27. Enter 4Kbit Mode (EN4K) Instruction Sequence
CS# 0 SCLK Instruction SI 1 2 3 4 5 6 7
High Impedance SO
Figure 28. Exit 4Kbit Mode (EX4K) Instruction Sequence
CS# 0 SCLK Instruction SI 1 2 3 4 5 6 7
High Impedance SO
Note: Enter and Exit 4kbit mode (EN4K & EX4K) EN4K and EX4K will not be executed when the chip is in busy state. Enter 4kbit mode then the read and write command will be executed on this 4kbit. All read and write command sequence is the same as the normal array. The address of this 4k bits is: A20~A9=0 and A8~A0 customer defined. Note 1: Chip erase and WRSR will not be executed in 4kbit mode Note 2: Chip erase can't erase this 4kbit About the fail status: Bit6 of the status register is used to state fail status, bit6=1 means program or erase have been failed. Any new write command will clear this bit.
P/N: PM1291
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Figure 29. READ ARRAY WAVEFORM (Parallel)
CS# SCLK SI PO7,PO6, ...PO0 CS# SCLK SI PO7,PO6, ...PO0 CS# SCLK SI PO7,PO6, ...PO0
............. Byte N
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit7
Bit6
Bit5
Bit4
Hi-Z 1st byte (03h) 2nd byte (AD1)
Bit1
Bit0
X .............
Byte 1
Byte 2
4th byte (AD3)
Hi-Z
NOTES: 1. 1st Byte='03h' 2. 2nd Byte=Address 1(AD1), AD23=BIT7, AD22=BIT6, AD21=BIT5, AD20=BIT4,....AD16=BIT0. 3. 3rd Byte=Address 2(AD2), AD15=BIT7, AD14=BIT6, AD13=BIT5, AD12=BIT4,....AD8=BIT0. 4. 4th Byte=Address 3(AD3), AD7=BIT7, AD6=BIT6, ....AD0=BIT0. 5. From Byte 5, SO Would Output Array Data. 6. Under parallel mode, the fastest access clock freq. will be changed to 1.2MHz(SCLK pin clock freq.). 7. To read array in parallel mode requires a parallel mode command (55H) before the read command. Once in the parallel mode, eLiteFlashTM Memory will not exit parallel mode until power-off. 8. In READ mode, RES mode and REMS mode, MXIC IC will enable output an entire cycle in advance compare with other compatible vendor's spec.
P/N: PM1291
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Figure 30. AUTO PAGE PROGRAM TIMING WAVEFORM (Parallel)
CS# SCLK SI PO7,PO6, ...PO0 CS# SCLK SI PO7,PO6, ...PO0 CS# SCLK SI PO7,PO6, ...PO0
............. Byte N
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit7
Bit6
Bit5
Bit4
Hi-Z 1st byte (02h) 2nd byte (AD1)
Bit1
Bit0
.............
Byte 1
Byte 2
4th byte (BA)
Hi-Z
NOTES: 1. 1st Byte='02h' 2. 2nd Byte=Address 1(AD1), AD23=BIT7, AD22=BIT6, AD21=BIT5, AD20=BIT4,....AD16=BIT0. 3. 3rd Byte=Address 2(AD2), AD15=BIT7, AD14=BIT6, AD13=BIT5, AD12=BIT4,....AD8=BIT0. 4. 4th Byte=Address 3(AD3), AD7=BIT7, AD6=BIT6, ....AD0=BIT0. 5. 5th byte: 1st write data byte. 6. Under parallel mode, the fastest access clock freq. will be changed to 1.2MHz(SCLK pin clock freq.). 7. To program in parallel mode requires a parallel mode command (55H) before the program command. Once in the parallel mode, eLiteFlashTM Memory will not exit parallel mode until power-off.
P/N: PM1291
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Figure 31. Read Identification (RDID) Instruction Sequence and Data-Out Sequence (Parallel)
CS# 0 SCLK Instruction SI Manufacturer Identification PO7~0 High Impedance
X
1
2
3
4
5
6
7
8
9 10
High Impedance Byte output Device Identification
NOTES: 1. Under parallel mode, the fastest access clock freg. will be changed to 1.2MHz(SCLK pin clock freg.) To read identification in parallel mode, which requires a parallel mode command (55H) before the read identification command. Once in the parallel mode, eLiteFlashTM Memory will not exit parallel mode until power-off. 2. Only 1~3 bytes would be output for manufacturer and Device ID. It's same for serial RDID mode. 3. In serial RDID and RDSR mode, output pin SO will be enabled at 8th clock's rising edge. That means, MXIC's drip will enable output half a cycle in advance compare with other compatible vendor's spec.
P/N: PM1291
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Figure 32. Release from Deep Power-down and Read Electronic Signature (RES) Instruction Sequence and Data-Out Sequence (Parallel)
CS# 0 SCLK Instruction 3 Dummy Bytes tRES2 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38
SI
23 22 21
3
2
1
0 Electronic Signature Out X Byte Output Deep Power-down Mode Stand-by Mode
High Impedance PO7~0
NOTES: 1. Under parallel mode, the fastest access clock freg. will be changed to 1.2MHz(SCLK pin clock freg.) To release from deep power-down mode and read ID in parallel mode, which requires a parallel mode command (55H) before the read status register command. Once in the parallel mode, eLiteFlashTM Memory will not exit parallel mode until power-off. 2. In READ mode, RES mode and REMS mode, MXIC IC will enable output an entire cycle in advance compare with other compatible vendor's spec.
P/N: PM1291
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Figure 33. READ STATUS REGISTER TIMING WAVEFORM (Parallel)
CS# SCLK SI PO7,PO6, ...PO0 CS# SCLK SI PO7,PO6, ...PO0
.............. Byte N
Bit7
Bit6
Bit0
..............
Hi-Z
X Byte 1 Byte 2
1st byte (05h)
Hi-Z
NOTES: 1. 1st Byte='05h' 2. BIT7 status register write disable signal. BIT7=1, means SR write disable. 3. BIT6=0 ==> Program/erase is correct. 4. BIT4, 3, 2 defines the level of protected block. (BIT 5 is not used) 5. BIT1 write enable latch 6. BIT0=0 ==> Device is in ready state 7. Under parallel mode, the fastest access clock freq. will be changed to 1.2MHz(SCLK pin clock freq.). To read status register in parallel mode requires a parallel mode command (55H) before the read status register command. Once in the parallel mode, eLiteFlashTM Memory will not exit parallel mode until power-off. 8. In serial RDID and RDSR mode, output pin SO will be enabled at 8th clock's rising edge. That means, MXIC's drip will enable output half a cycle in advance compare with other compatible vendor's spec.
P/N: PM1291
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Figure 34. Read Electronic Manufacturer & Device ID (REMS) Instruction Sequence and Data-Out Sequence (Parallel)
CS# 0 SCLK Instruction 2 Dummy Bytes 1 2 3 4 5 6 7 8 9 10
SI
15 14 13
3
2
1
0
PO7~0
High Impedance
CS# 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK ADD (1)
SI
7
6
5
4
3
2
1
0 Manufacturer ID
PO7~0
X
Device ID
NOTES: (1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first (2) Under parallel mode, the fastest access clock freg. will be changed to 1.2MHz(SCLK pin clock freg.) To read ID in parallel mode, which requires a parallel mode command (55H) before the read ID command. Once in the parallel mode, eLiteFlashTM Memory will not exit parallel mode until power-off. (3) In READ mode, RES mode and REMS mode, MXIC IC will enable output an entire cycle in advance compare with other compatible vendor's spec.
P/N: PM1291
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RECOMMENDED OPERATING CONDITIONS
At Device Power-Up AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly.
VCC(min)
VCC
GND tVR tSHSL
CS#
tCHSL tSLCH tCHSH tSHCH
SCLK
tDVCH tCHDX tCLCH LSB IN tCHCL
SI
MSB IN
SO
High Impedance
Figure A. AC Timing at Device Power-Up
Symbol tVR
Parameter VCC Rise Time
Notes 1
Min. 0.5
Max. 500000
Unit us/V
Notes : 1. Sampled, not 100% tested. 2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "AC CHARACTERISTICS" table.
P/N: PM1291
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ERASE AND PROGRAMMING PERFORMANCE
PARAMETER Chip Erase Time Chip Erase Time (with ACC=12V) Sector erase Time Sector erase Time (with ACC=12V) Additional 4Kb Erase Time Page Programming Time Page Programming Time (with ACC=12V) Erase/Program Cycle Main Array Additional 4Kb 10K 100K cycles cycles 25 3 2.4 50 12 9.6 mS mS mS Note (4) Excludes system level overhead(3) 1 0.8 3 2.4 s s Note (4) Note (4) Min. TYP. (1) 32 25 Max. (2) 64 52 UNIT s s Note (4) Comments
Note: 1. Typical program and erase time assumes the following conditions: 25C, 3.0V, and all bits are programmed by checkerboard pattern. 2. Under worst conditions of 70C and 3.0V. Maximum values are up to including 10K program/erase cycles. 3. System-level overhead is the time required to execute the command sequences for the page program command. 4. Excludes 00H programming prior to erasure. (In the pre-programming step of the embedded erase algorithm, all bits are programmed to 00H before erasure)
LATCH-UP CHARACTERISTICS
MIN. Input Voltage with respect to GND on ACC Input Voltage with respect to GND on all power pins, SI, CS# Input Voltage with respect to GND on SO Current Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. -1.0V -1.0V -1.0V -100mA MAX. 12.5V 2 VCCmax VCC + 1.0V +100mA
P/N: PM1291
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ORDERING INFORMATION
PART NO. MX25L1605ZMC-20G MX25L1605ZMI-20G ACCESS TIME(ns) 20 20 OPERATING CURRENT(mA) 30 30 STANDBY CURRENT(uA) 50 50 0~70C -40~85C 8-land SON 8-land SON Pb-free Pb-free Temperature PACKAGE Remark
P/N: PM1291
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PART NAME DESCRIPTION
MX 25 L 1605 ZM C 20 G
OPTION: G: Pb-free blank: normal SPEED: 20: 50MHz, for SPI
TEMPERATURE RANGE: C: Commercial (0C to 70C) I: Industrial (-40C to 85C)
PACKAGE: ZM: SON
DENSITY & MODE: 1605: 16Mb
TYPE: L: 3V
DEVICE: 25: Serial Flash
P/N: PM1291
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PACKAGE INFORMATION
P/N: PM1291
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MACRONIX INTERNATIONAL CO., LTD.
Headquarters:
TEL:+886-3-578-6688 FAX:+886-3-563-2888
Europe Office :
TEL:+32-2-456-8020 FAX:+32-2-456-8021
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TEL:+86-755-834-335-79 FAX:+86-755-834-380-78
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TEL:+81-44-246-9100 FAX:+81-44-246-9105
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TEL:+65-6346-5505 FAX:+65-6348-8096
Taipei Office :
TEL:+886-2-2509-3300 FAX:+886-2-2509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-262-8887 FAX:+1-408-262-8810
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.

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